1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to the formation of features having critical dimensions, such as gate electrode structures, in modem ultra high density integrated circuits.
2. Description of the Related Art
Fabrication of integrated circuits requires tiny regions of precisely controlled size to be formed in a material layer of an appropriate substrate, such as a silicon substrate. These tiny regions of precisely controlled size are generated by treating the material layer by means of, for example, ion implantation or etching, wherein a mask layer is formed over the material layer to be treated to define these tiny regions. A particularly critical step in defining such tiny regions is, for example, the formation of gate electrodes of field effect transistors. Such gate electrodes are substantially comprised of a polycrystalline silicon feature line having a lateral dimension of 0.18 μm and smaller in modem integrated circuits.
In general, the mask layer used for patterning device features may consist of or is formed by means of a layer of photoresist that is patterned by a lithographic process. During the lithographic process, the resist may be spin coated onto the wafer substrate, and is then selectively exposed to ultraviolet radiation. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions of the photoresist are removed to form the required pattern in the photoresist layer. Since the dimensions of the patterns in modern integrated circuits are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution of the involved processes for forming these features. In this respect, resolution is considered as a measure specifying the consistent ability to print minimum-size images under conditions of predefined manufacturing variations. Since printing of features onto a substrate requires a plurality of interrelated processes, such as coating the substrate with a photoresist exhibiting defined optical characteristics as well as a defined resistance to an etchant, exposing the substrate to radiation, developing the exposed photoresist, wherein developing involves various tempering steps, and etching the substrate (for example, when forming gate electrodes), the resolution of features, i.e., a minimum distance between adjacent features or a minimal feature width, is not exclusively determined by the quality of the imaging process, but also by the subsequent etch process, especially when features are formed, having dimensions less than the wavelength of the radiation used for irradiating the photoresist.
One important factor in improving the resolution is represented by the lithographic process, in which patterns contained in a photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus, and wavelength of the light source used.
The quality of the lithographic imagery is extremely important in creating very small feature sizes. Of comparable importance is, however, the accuracy with which an image can be positioned on the surface of the substrate. Integrated circuits are fabricated by sequentially patterning material layers, wherein features on successive material layers bear a spatial relationship to one another. Each pattern formed in a subsequent material layer has to be aligned to a corresponding pattern formed in the previous material layer within specified registration tolerances. These registration tolerances are caused by, for example, a variation of a photoresist image on the substrate due to non-uniformities in such parameters as resist thickness, baking temperature, exposure intensity and development characteristics. Furthermore, non-uniformities in the etch processes may lead to variations of the etched features. Modem integrated circuits are designed to include gate electrodes having a lateral dimension, also referred to as gate length, that is comparable to and even smaller than the wavelength of the photolithography tool used. To this end, a so-called trim etch process is employed to form features of lateral dimensions beyond the optical resolution, which significantly contributes to the overall resolution of the patterning process thus playing a dominant role for the quality of the features formed.
Accordingly, it is essential to steadily monitor the resolution, i.e., the capability of reliably and reproducibly creating the minimum feature size, also referred to as critical dimension (CD), within a specific material layer. To this end, typically, two or three wafers per lot, having formed thereon a photoresist pattern, are subjected to a scanning electron microscope analysis (SEM) to monitor the quality of the imaging process including photoresist treatment and development parameters. The analysis may yield measurement results regarding resist uniformity, critical dimensions of the resist features, steepness of the sidewalls of resist feature lines, and the like. Additionally, two or three wafers per lot are subjected to SEM analysis after completion of the etch process to monitor the overall resolution, i.e., the critical dimension, of the patterning process. Depending on the results of these measurements, the parameter values of the parameters defining the photolithography step and the etch process may be correspondingly re-adjusted to try maintaining the critical dimensions within allowed tolerances set by the design rules. Owing to gathering information on the quality of the patterning process in a random test-like fashion, process variations can at best be compensated on a lot basis, for example, by re-adjusting corresponding process parameters, wherein variations within a lot due to variations within the substrates or changes of the process tools are not detectable.
Since the quality of features with critical dimensions, such as gate electrodes, is important for the entire device in view of functionality as well as with respect to economical reasons (throughput), it is highly desirable to improve the process of patterning of features with critical dimensions with respect to both accuracy and robustness of the patterning process.